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1 for more information www.linear.com/ltc3870 typical a pplica t ion fea t ures descrip t ion polyphase step-down slave controller for ltc 3880/ ltc 3883 with digital power system management the lt c ? 3870 is a polyphase ? step-down slave control- ler specially designed for multiphase operation with the ltc3880 and ltc3883 digital power system management dc/dc controllers. it provides a small and cost effective solution for supplying very large currents by cascading it with a ltc3880 or ltc3883 controller. a peak current mode architecture provides the ltc3870 with excellent current sharing from phase to phase and from chip to chip. coherently working with the ltc3880 or ltc3883, the ltc3870 does not require additional i 2 c addresses, and it supports all programmable features as well as fault protection. the constant switching frequency can be synchronized to an external clock from the ltc3880 or ltc3883 from 100 khz to 1mhz. load transient response of a 2-phase master (3880)/slave (3870) converter a pplica t ions n ltc3880/ltc3883 phase extender n cascade with multiple chips for very large current applications n accurate polyphase current sharing n extv cc capable of 5v to 14v input n wide v in range: 4.5v to 60v n wide output voltage range : 0.5v to 14v n wide sync frequency range: 100khz to 1mhz n pin programmable of ccm/dcm operation n pin programmable of phase-shift control n integrated powerful n-channel mosfet gate drivers n available in a 28-pin (4mm 5mm) qfn package n high power distributed power systems n telecom systems n industrial applications l, lt , lt c , lt m , polyphase, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 5408150 + + v in 4.7f boost0 sw0 bg0 boost1 tg0 tg1 sw1 bg1 freq * refer to ltc3880 data sheet for master setup ltc3870 i lim phasmd mode0 mode1 sgnd run0 sync run1 fault0 fault1 pgnd 0.1f 0.1f 1.0h 0.56h 0.2f 0.2f run0 gpio0 gpio1 run1 sync i th0 i th1 3.3v v sense0 + i sense0 + i sense0 ? i sense1 + i sense1 ? i th0 i th1 v sense1 ltc3880* 1.8v 2.15k 1.74k 100k 530f 530f v out0 30a v out1 40a v in intv cc extv cc 3870 ta01a v in = 12v v out1 = 1.8v 50s/div 3870 ta01b i l_3880(ch1) 10a/div i l_3870(ch1) 10a/div v out1 100mv/div ac-coupled i load 10a/div 0a to 10a to 0a ltc 3870 3870fa
2 for more information www.linear.com/ltc3870 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in ............................................................. C0.3 v to 65 v boost 0, boost1 ....................................... C0.3 v to 71 v sw 0, sw1 .................................................... C5 v to 65 v i sense 0 + , i sense 0 ? , i sense 1 + , i sense 1 C ..........C0.3 v to 15 v (boost 0- sw 0), ( boost 1- sw 1) ................. C0.3 v to 6v in tv cc , run 0/ run 1 ................................... C0.3 v to 6v ex tv cc ...................................................... C0.3 v to 14 v mode 0/ mode 1, freq , phasmd , i lim ... C0.3 v to intv cc fau lt 0 / fau lt 1 , i th 0 /i th 1 , sync .............. C0.3 v to 3. 6 v intv cc , extv cc peak current ( note 9) ............... 100 ma oper ating junction temperature range .......................................................... C40 c to 125 c storage temperature range .................. C65 c to 150 c 9 10 top view ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 mode0 i sense0 + i sense0 ? run0 run1 i sense1 ? i sense1 + mode1 boost0 bg0 v in pgnd extv cc intv cc bg1 boost1 i th0 freq fault0 fault1 tg0 sw0 i th1 i lim sync phasmd tg1 sw1 7 17 18 19 20 21 22 16 8 15 29 sgnd t jmax = 125c, v ja = 43c/w, v jc_bot = 3.4c/w exposed pad (pin 29) is sgnd, must be soldered to pcb o r d er i n f or m a t ion e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v in input voltage range (note 3) 4.5 60 v v out output voltage range (note 4) 0.5 14 v i q input voltage supply current normal operation v run0, v run1 = 0v ( note 5) v run0, v run1 = 3.3v , no caps on tg and bg 1.1 2.6 ma ma v uvlo undervoltage lockout threshold when v in > 4.2v v intvcc falling v intvcc rising 3.7 4.0 v v the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) v in = 15v, v run0, v run1 = 3.3v, f sync = 350khz (externally driven) unless otherwise specified. lead free finish tape and reel part marking* package description temperature range ltc3870eufd#pbf ltc3870eufd#trpbf 3870 28-lead (4mm w 5mm) plastic qfn C40c to 125c ltc3870iufd#pbf ltc3870iufd#trpbf 3870 28-lead (4mm w 5mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. * the temperature grade is identified by a label on the shipping container . consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ (note 1) ltc 3870 3870fa
3 for more information www.linear.com/ltc3870 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) v in = 15v, v run0, v run1 = 3.3v, f sync = 350khz (externally driven) unless otherwise specified. symbol parameter conditions min typ max units control loop i isense0 + , i isense1 + current sense + pin current v isense0,1 + = 3.3v l 0.1 1 a i isense0 C , i isense1 C current sense ? pin current v isense0,1 C = 3.3v l 0.1 1 a v iilimit maximum current sense threshold (high range) v ith = 2.22v, i lim = intv cc l 70 75 80 mv maximum current sense threshold (low range) v ith = 2.22v, i lim = gnd l 45 50 55 mv gate drivers tg r up pull-up on-resistance tg high 2.5 tg r down pull-down on-resistance tg low 1.5 bg r up pull-up on-resistance bg high 2.4 bg r down pull-down on-resistance bg low 1.1 tg0, tg1 t r t f tg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 30 30 ns ns bg0, bg1 t r t f bg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 30 30 ns ns tg/bg t 1d top gate off to bottom gate on delay time (note 6) c load = 3300pf each driver 30 ns bg/tg t 2d bottom gate off to top gate on delay time (note 6) c load = 3300pf each driver 30 ns t on(min) minimum on-time (note 7) 90 ns intv cc regulator v intvcc_vin internal v cc voltage no load 6.0v 4 for more information www.linear.com/ltc3870 typical p er f or m ance c harac t eris t ics efficiency vs load current efficiency vs load current full load efficiency and power loss vs input voltage e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) v in = 15v, v run0, v run1 = 3.3v, f sync = 350khz (externally driven) unless otherwise specified. note 1: stresses beyond those listed in under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3870 is tested under pulsed load conditions such that t j t a . the ltc3870e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40? to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3870i is guaranteed over the full C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the related package thermal impedance and other environmental factors. the junction temperature t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? 43c/w) note 3: when v in >15v, extv cc is recommended to reduce ic temperature. note 4: output voltage is set and controlled by the ltc3880/ltc3883 in multiphase operations. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see application information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: the minimum on-time condition corresponds to an inductor peak-to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section. note 8: extv cc is enabled only if v in is higher than 6.5v. note 9: guaranteed by design. symbol parameter conditions min typ max units digital inputs run0/run1, mode0/mode1, fau lt0/ fau lt1 v ih input high threshold voltage l 2.0 v v il input low threshold voltage l 1.4 v load current (a) 0.1 0 efficiency (%) 80 70 90 60 50 40 30 20 10 100 1 10 100 3870 g01 ccm dcm v in = 12v v out = 1.8v f sw = 400khz l = 0.56h dcr = 1.8m load current (a) 0.1 0 efficiency (%) 80 70 90 60 50 40 30 20 10 100 1 10 100 3870 g02 ccm dcm v in = 12v v out = 3.3v f sw = 400khz l = 0.56h dcr = 1.8m input voltage (v) 5 87 efficiency (%) power loss (w) 93 92 91 90 89 88 94 0 2.5 2 1.5 1 0.5 3 7 9 11 13 15 17 19 3870 g03 efficiency power loss v in = 12v v out = 1.8v ltc 3870 3870fa
5 for more information www.linear.com/ltc3870 typical p er f or m ance c harac t eris t ics load step ( discontinuous conduction mode) 4-phase operation ltc3880 and ltc3870 load step (forced continuous mode) 4-phase operation ltc3880 and ltc3870 inductor current at light load start-up into a pre-biased output 4-phase operation ltc3880 and ltc3870 current sense threshold vs i th voltage intv cc line regulation dc output current matching between ltc3880 and ltc3870 dynamic current sharing during a load transient in a 4-phase operation ltc3880 and ltc3870 quiescent current vs input voltage without extv cc v ith (v) 0 ?40 v isense (mv) 60 40 20 0 ?20 80 0.5 1 1.5 2 2.5 3870 g08 range low range high input voltage (v) 0 0 intv cc voltage (v) 4 5 3 2 1 6 2010 30 40 50 60 3870 g09 input voltage (v) 0 0 supply current (ma) 2.5 3 2 1.5 1 0.5 3.5 2010 30 40 50 60 3870 g12 1s/div i l_3870(ch0) forced continuous mode 5a/div i l_3870(ch0) discontinuous conduction mode 5a/div 3870 g06 v in = 12v v out = 1.8v i load = 1a 2ms/div run all run pins tied together 2v/div v out ltc3870 in dcm 500mv/div 3870 g07 v in = 12v v out = 1.8v total output current (a) 0 0 channel current (a) 20 15 10 5 25 10 20 30 40 50 60 70 80 90 3870 g10 ltc3870 ch1 ltc3870 ch0 ltc3880 ch1 ltc3880 ch0 50s/div i l_3880(ch0) i l_3880(ch1) i l_3870(ch0) i l_3870(ch1) 5a/div 3870 g11 i load 0a to 32a to 0a 50s/div i load 20a/div 0a to 20a to 0a i l_3880(ch0) 10a/div i l_3870(ch0) 10a/div v out 100mv/div ac-coupled 3870 g04 v in = 12v v out = 1.8v 50s/div i load 20a/div 0a to 20a to 0a i l_3880(ch0) 10a/div i l_3870(ch0) 10a/div v out 100mv/div ac-coupled 3870 g05 v in = 12v v out = 1.8v ltc 3870 3870fa
6 for more information www.linear.com/ltc3870 p in func t ions mode0/mode 1 (pin 1/pin 8): dcm/ccm mode control pins. channel0/channel1 operates in forced continuous mode if mode0/mode1 pin is logic high. there is a 500 k pull down resistor on mode0/mode1 internally. the default operation mode in each channel is discontinuous mode operation unless these pins are actively driven high. i sense0 + /i sense1 + ( pin 2/pin 7): current sense comparator positive inputs, normally connected to the positive node of the dcr sensing networks or current sensing resistors. i sense0 ? /i sense1 ? ( pin 3/pin 6): current sense comparator negative inputs, normally connected to the negative node of the dcr sensing network or current sensing resistors. run0/run1 (pin 4/pin 5): enable run input pins. logic high on these pins enables the corresponding channel. in multiphase operation, these pins are connected to ltc3880/ltc3883 run pins. i th0 /i th1 ( pin 28/pin 9): current control threshold. each associated channel s current comparator tripping threshold increases with its i th voltage. in multiphase operation, these pins are connected to the master controllers i th pins for current sharing. i lim ( pin 10): program current comparators sense voltage range. this pin can be tied to sgnd or intv cc to select the maximum current sense threshold for each current comparator. sgnd sets both channels current low range with maximum 50 mv sensing voltage. intv cc sets both channels current high range with maximum 75mv sensing voltage. for equal current sharing, the setup on the i lim pin has to be same as the setup on the bit 7 of mfr_ pwm_ mode_ 3880/3883 register in the master controller. see table 2 in the operation section for details. sync (pin 11): external clock synchronization input. if an external clock is present at this pin, the switching frequency will be synchronized to the falling edge of the external clock. in multiphase operation, this pin is con - nected to ltc3880/ltc3883 the sync pin for frequency synchronization. do not float the sync pin. phasmd (pin 12): phase set pin. this pin can be tied to sgnd, intv cc or a resistor divider from intv cc to sgnd. this pin determines the relative phases between the ext - ernal clock on the sync pin and the internal controllers. see table 1 in the operation section for details. tg0/tg1 (pin 24/pin 13): top gate driver outputs. these are the outputs of floating drivers with a voltage swing equal to intv cc superimposed on the switch node voltages. sw0/sw 1 (pin 23/pin 14): switch node connections to inductors. voltage swings at the pins are from a schottky diode (external) voltage drop below ground to v in . boost0/boost1 (pin 22/pin 15): boosted floating driver supplies. the (+) terminal of the bootstrap capacitors con - nect to these pins. these pins swing from a diode voltage drop below intv cc up to v in + intv cc . bg0/bg1 (pin 21/pin 16): bottom gate driver outputs. these pins drive the gates of the bottom n-channel mos - fets between pgnd and intv cc . intv cc ( pin 17): internal regulator 5 v output. the internal control circuits are powered from this voltage. bypass this pin to pgnd with a minimum of 4.7 f low esr tantalum or ceramic capacitor. intv cc is enabled as soon as v in is powered. extv cc (pin 18): external power input to an internal ldo connected to intv cc . this ldo supplies intv cc power bypassing the internal ldo powered from v in whenever extv cc is higher than 4.8 v. see extv cc connection in the applications information section. do not exceed 14 v on this pin. bypass this pin to pgnd with a minimum of 4.7f low esr tantalum or ceramic capacitor. if the extv cc pin is not used, leave it open or tie it to ground. extv cc can be present before v in . however, extv cc is enabled only if v in is higher than 6.5v. pgnd ( pin 19): power ground pin. connect this pin closely to the sources of the bottom n-channel mosfets and the (C) terminals of c in . v in (pin 20): main input supply. bypass this pin to pgnd with a capacitor (0.1f to 1f). ltc 3870 3870fa
7 for more information www.linear.com/ltc3870 fau lt0/ fau lt1 (pin 26/pin 25): fault input pins. con- nect these pins to the master chip gpio pins to respond to fault signals from the master controller. if this pin is low, both tg and bg pins are pulled down at the corre - sponding channel. there is a 500k pull down resistor on fau lt0/ fau lt1 internally. these pins have to be driven high externally for normal operation. freq (pin 27): frequency set pin. there is a precision 10a current flowing out of this pin. a resistor to ground sets a voltage which in turn programs the frequency. this p in func t ions pin sets the default switching frequency when there is no external clock on the sync pin. set the frequency close to the external clock to help the internal pll sync to the sync pin clock quickly and smoothly. see the application section for the detailed information. sgnd ( exposed pad pin 29): signal ground. all small- signal and compensation components should connect to this ground, which in turn connects to pgnd at one point. the exposed pad must be soldered to the pcb, providing a local ground for the control components of the ic, and be tied to pgnd under the ic. ltc 3870 3870fa
8 for more information www.linear.com/ltc3870 b lock diagra m 11 12 18 10 1 4 26 29 28 10a sync phasmd extv cc intv cc intv cc i rev i cmp intv cc i th0 i lim i sense0 + i sense0 ? c b d b c vcc boost0 m1 l on 3k rev uvlo fcnt run faultb m2 sgnd 1.7v run0 mode0 fault0 tg0 sw0 bg0 pgnd v in v in v out0 c out0 c in 4.8v freq c c r c 24 21 27 20 17 22 23 19 2 3 sync det phase program osc pfd vco uvlo slope compensation i lim range select hi: 1:1 lo: 1:1.5 switch logic and anti- shoot- through s r q 5.0v ldo en 5.0v ldo en + + ref + ? ? + ? + + ? + ? + ? 3870 bd 1 71.1k (ch0 shown) ltc 3870 3870fa
9 for more information www.linear.com/ltc3870 o pera t ion main control loop the ltc3870 is a constant frequency, current mode step-down slave controller for parallel operation with the ltc3880/ltc3883. during normal operation, each top mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the main current comparator, icmp, resets the rs latch. the peak inductor current at which icmp resets the rs latch is controlled by the voltage on the i th pin, which is tied directly to the corresponding i th pin of the master controllers (ltc3880/ ltc3883). when the load current increases, ltc3880/ ltc3883 master controllers drive and increase the i th voltage, which in turn cause the peak current in the cor- responding slave channels to increase, until the average inductor current matches the new load current. after the top mosfet has been turned off, the bottom mosfet is turned on until the beginning of the next cycle in continu - ous conduction mode (ccm) or until the inductor current starts to reverse, as indicated by the reverse current comparator i rev , in discontinuous conduction mode (dcm). the ltc3870 slave controllers do not regulate the output voltage but regulate the current in each channel for current sharing with master controllers. output voltage regulation is achieved through the voltage feedback loops in master controllers. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. normally an internal 5.0 v linear regulator supplies intv cc power from v in . in high v in applications, if a high effi- ciency external voltage source is available for the extv cc pin, another internal 5.0v linear regulator is enabled and supplies intv cc power from extv cc . to enable the linear regulator driven by the extv cc pin, v in has to be higher than 6.5 v and extv cc pin voltage has to be higher than 4.8v. do not exceed 14v on the extv cc pin. each top mosfet driver is biased from the floating bootstrap capacitor c b , which normally recharges during each off cycle through an external diode when the top mosfet turns off. if the input voltage v in decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about one-twelfth of the clock period plus 100ns every three cycles to allow c b to recharge. however, it is recommended that a load be present or the ic operates at low frequency during the drop-out transition to ensure c b is recharged. start-up and shutdown (run0, run1) the two channels of the ltc3870 can independently start up and shut down using the run0 and run1 pins. pulling either of these pins below 1.4 v shuts down the control circuits for that channel. during shutdown, both tg and bg are pulled down to turn off the external power mosfets. pulling either of these pins above 2 v enables the corresponding channel and internal circuits. during startup, the run0/run1 pins are actively pulled down until the intv cc voltage passes the under-voltage lockout threshold of 4 v. for multiphase parallel operation, the run0/run1 pins have to be connected and driven by the run pins of the master controller. do not exceed the absolute maximum rating of 6v on these pins. the start-up of each channels output voltage v out is controlled and programmed by the master controller. after the run pins are released, the master controller drives the output based on the programmed delay time and rise time, and the slave controller ltc3870 just follows the master to supply equivalent current to the output during startup. light load current operation (discontinuous conduction mode, continuous conduction mode) the ltc3870 can be set to operate either in discontinuous conduction mode ( dcm) or forced continuous conduc - tion mode (ccm). to select for ced continuous mode of operation, tie the mode pin to a dc voltage above 2v (e.g., intv cc ). to select discontinuous conduction mode of operation, tie the mode pin to a dc voltage below 1.4v (e.g., sgnd). in forced continuous operation, the induc - tor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the i th pin. in this mode, the efficiency at light loads is lower than in discontinu- ous mode operation. however, continuous mode has the advantages of lower output ripple and less interference ltc 3870 3870fa
10 for more information www.linear.com/ltc3870 with audio circuitry. when the mode pin is connected to sgnd, the ltc3870 operates in discontinuous mode at light loads. at very light loads, the current comparator icmp may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles ( i.e., skipping pulses). this mode provides higher light load efficiency than forced continuous mode and the inductor current is not allowed to reverse. there are 500k pull down resistors internally connected to the mode0/ mode1 pins. if mode0/mode1 pins are floating, both channels default to discontinuous conduction mode. multichip operation (phasmd and sync pins) the phasmd pin determines the relative phases between the internal channels as well as the external clock signal on the sync pin, as shown in table 1. the phases tabulated are relative to zero degree phase being defined as the falling edge of the clock on sync. table 1. phasmd channel 0 phase channel 1 phase gnd 180 0 1/3 intv cc 60 300 2/3 intv cc or float 120 240 intv cc 90 270 the sync pin is used to synchronize switching frequency between master and slave controllers. input capacitance esr requirements and efficiency losses are substantially reduced because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the rms current squared. a two-phase, single output voltage implementa - tion can reduce input path power loss by 75% and radi- cally reduce the required rms current rating of the input capacitor(s). o pera t ion single output multiphase operation the ltc3870 is designed for multiphase converters with ltc3880/ltc3883 by making these connections: ? tie all the i th pins of paralleled channels together for current sharing between masters and slaves. note that i lim setup on slaves has to match mfr_pwm_mode current range setup in masters. ? tie all sync pins together between master and slaves for same switching frequency synchronization; one and only one of the ltc3880/ltc3883 controllers has to be programmed as master to generate clock signal on the sync pin. ? tie all the run pins of paralleled channels together between master and slaves for startup and shutdown sequences. ? tie the gpio pin of the master controller to the fault pin of slave controllers and program the master gpio as fault sharing for fault protections. examples of single output multiphase converters are shown in figure 1. inductor current sensing like the ltc3880 / ltc3883, ltc3870 can use either induc - tor dcr or r sense to sense the inductor current. inductor dcr current sensing provides a lossless method of sens- ing the instantaneous current. therefore, it can provide higher efficiency for applications with high output currents. however, the dcr of a copper inductor typically has 10% tolerance. for precise current sensing, a precision sensing resistor r sense can be used to sense the inductor current. it is important to match the current sensing circuit between master controllers and slave controllers to guarantee bal - anced load sharing and overcurrent protection. ltc 3870 3870fa
11 for more information www.linear.com/ltc3870 o pera t ion ltc3880 0 180 ltc3880 0 180 ltc3870 180 0 ltc3870 120 240 phasmd = gnd 2 + 2 1 + 3 6 phase operation 4 phase operation phasmd = 2/3 intv cc or float ch0 ch1 ch0 ch1 ch0 ch1 ch0 ch1 ltc3880 0 180 ltc3870 90 270 phasmd = intv cc ch0 ch1 ch0 ch1 ltc3870 60 300 ltc3880 0 180 phasmd = 1/3 intv cc phasmd = 2/3 intv cc ch0 ch1 ch0 ch1 ltc3870 120 240 ch0 ch1 3870 f01 frequency selection and phase-locked loop (freq and sync pins) the selection of switching frequency is a trade- off between efficiency and component size. low frequency operation increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to main - tain low output ripple voltage. the switching frequency of the ltc3870 controllers can be synchronized to the falling edge of the external clock on the sync pin or selected us - ing the freq pin. a phase-locked loop ( pll) is integrated in the ltc3870 to synchronize the internal oscillator to an external clock source that is connected to the sync pin; this source is normally provided by the master control - lers. the pll loop filter network is integrated inside the figure 1. examples of single/dual output multiphase converters ltc3870. the phase-locked loop is capable of locking to any frequency within the range of 100khz to 1mhz. if the sync pin is not being driven by an external clock source, the freq pin can be used to program the ltc3870 s operating frequency from 100 khz to 1 mhz. there is a precision 10 a current flowing out of the freq pin, so the user can program the controller s switching frequency with a single resistor to sgnd. a curve is provided later in the application section showing the relationship between the voltage on the freq pin and switching frequency. the frequency setting resistor should always be present to set the controllers initial switching frequency before locking to the external clock. ltc 3870 3870fa
12 for more information www.linear.com/ltc3870 the typical application on the first page of this data sheet is a basic ltc3870 application circuit featuring the ltc3880 as a slave controller. in paralleled operation, the current sensing scheme as well as the power stage parameters in ltc3870 must be the same as the master controller to achieve balanced current sharing between masters and slaves. finally, input and output capacitors are selected based on rms current rating, ripple, and transient specs. current limit programming to match the master controller current limit, each chan - nel of ltc3870 can be programmed separately with two current ranges. the i lim pin of ltc3870 is a 4- level logic input which sets the current limit of ltc3870. when i lim is grounded, both channel0 and channel1 are set to be low current range. when i lim is tied to intv cc , both channel0 and channel1 are set to be high current range. here, low current range means the current sense threshold linearly increases from 0 mv to 50 mv as i th voltage is increased from 0.5 v to 2.22 v without slope compensation. high cur- rent range means the current sense threshold increases to 75mv as i th voltage is increased to 2.22 v without slope compensation. set i lim to one-third intv cc for channel0 high current range and channel1 low current range. set i lim to two-thirds intv cc or float for channel0 low current range and channel1 high current range. the summary of i lim pin setups is shown in table 2. for balanced load current sharing, use the same current range setting as in the master controller. note that the ltc3870 does not have active clamping circuit on i th pin for peak current limit and over current protection. over current protection relies on the master controller to drive and clamp the i th pin voltage not to exceed the programmed voltage through the pmbus command. table 2. i lim channel 0 current limit channel 1 current limit gnd range low range low 1/3 intv cc range high range low 2/3 intv cc or float range low range high intv cc range high range high a pplica t ions i n f or m a t ion intv cc regulators and extv cc the ltc3870 features a pmos ldo that supplies power to intv cc from the v in supply. intv cc powers the gate drivers and most of the ltc3870s internal circuitry. the linear regulator regulates the voltage at the intv cc pin to 5.0 v when v in is greater than 6 v. extv cc connects to intv cc through another pmos ldo and can supply the needed power when its voltage is higher than 4.8 v and v in is higher than 6.5 v. each of these ldos can supply a peak current of 100 ma and must be bypassed to ground with a minimum of 4.7 f ceramic capacitor or low esr electrolytic capacitor. no matter what type of bulk capaci - tor is used, an additional 0.1 f ceramic capacitor placed directly adjacent to the int v cc and pgnd pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maximum junction temperature rating for the ltc3870 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the 5.0 v linear regula- tor from v in or the linear regulator from extv cc . when the voltage on the extv cc pin is less than 4.8 v, the linear regulator from v in is enabled. power dissipation for the ic in this case is highest and is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency. the junction temperature can be estimated by using the equations given in note 2 of the electrical characteristics. for example, the ltc3870 intv cc current is limited to less than 34 ma from a 38 v supply in the ufd package and not using the extv cc supply: t j = 70c + (34ma)(38v)(43c/w) = 125c where ambient temperature is 70 c and thermal resistance from junction to ambient is 43c/w. to prevent the maximum junction temperature from be - ing exceeded, the input supply current must be checked while operating in continuous conduction mode (mode = intv cc ) at maximum v in . when the voltage applied to extv cc rises above 4.8 v and v in above 6.5 v, the intv cc linear regulator is turned off and the extv cc linear regulator is turned on. using the extv cc allows the mosfet driver ltc 3870 3870fa
13 for more information www.linear.com/ltc3870 and control power to be derived from other high efficiency sources such as +5 v or +12 v rails in the system. using extv cc can significantly reduce the ic temperature in high v in applications. tying the extv cc pin to a 5 v supply reduces the junction temperature in the previous example from 125 c to: t j = 70c + (34ma) (5v) (43c/w) = 77c. do not apply more than 14v to the extv cc pin. for applications where the main input power is 5 v, tie the v in and intv cc pins together and tie the combined pins to the 5 v input with a 1 or 2.2 resistor as shown in figure 2 to minimize the voltage drop caused by the gate charge current. this will override the intv cc linear regulator and will prevent intv cc from dropping too low due to the dropout voltage. make sure the intv cc voltage is at or exceeds the r ds(on) test voltage for the mosfet which is typically 4.5v for logic-level devices. a pplica t ions i n f or m a t ion the final arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the efficiency has improved. if there is no change in input current, then there is no change in efficiency . undervoltage lockout the ltc3870 has a precision uvlo comparator constantly monitoring the intv cc voltage to ensure that an adequate gate-drive voltage is present. it locks out the switching action and pulls down run pins when intv cc is below 3.7v. to prevent oscillation when there is a disturbance on the intv cc , the uvlo comparator has 300 mv of precision hysteresis. in multiphase operation, when ltc3870 is in undervoltage lockout, the run0 and run1 pins are pulled down to disable the masters switching action. phase-locked loop and frequency synchronization the ltc3870 has a phase-locked loop ( pll) comprised of an internal voltage-controlled oscillator ( vco) and a phase detector. this allows the internal clock to be locked to the falling edge of an external clock signal applied to the sync pin. the turn-on of channel 0/channel 1 s top mosfet is synchronized or out-of-phase with the falling edge of the external clock. the phase detector is an edge sensitive digital type that provides zero degree phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complementary current sources that charge or discharge the internal filter network. there is a precision 10 a of current flowing out of the freq pin. this allows the user to use a single resistor to sgnd to set the switching frequency when no external clock is applied to the sync pin. the voltage on the freq pin is equal to the resistance multiplied by 10a current (e.g. the voltage is 1 v with a 100 k resistor from the freq pin to sgnd). the internal switch between freq pin and the integrated pll filter network is on, allowing the filter network to be pre-charged to the same voltage potential as the freq pin. the relationship between the voltage on the freq pin and the operating frequency is shown in figure 3 and specified in the electrical characteristic table. if an external clock is detected on the sync pin, the internal switch mentioned above will turn off and isolate 3870 f04 v in c in c intvcc 4.7f r vin 1 intv cc ltc3870 5v + figure 2. setup for a 5v input topside mosfet driver supply (cb, db) external bootstrap capacitor c b , connected to the boost pin, supplies the gate drive voltages for the topside mos- fet. capacitor c b in the functional diagram is charged though external diode db from intv cc when the sw pin is low. when the topside mosfet is to be turned on, the driver places the c b voltage across the gate source of the mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc C v db the value of the boost capacitor, c b , needs to be 100 times that of the total input capacitance of the topside mosfet (s ). the reverse breakdown of the external schottky diode must be greater than v in( max) . when adjusting the gate drive level, ltc 3870 3870fa
14 for more information www.linear.com/ltc3870 a pplica t ions i n f or m a t ion the influence of freq pin. note that the ltc3870 can only be synchronized to an external clock whose frequency is within the range of the ltc3870s internal vco. this is guaranteed to be between 100 khz and 1 mhz. a simplified block diagram is shown in figure 4. if the external clock frequency is greater than the inter - nal oscillators frequency, f osc , then current is sourced continuously from the phase detector output, pulling up the filter network. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the filter network. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the filter network is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the filter capacitor holds the voltage. typically, the external clock ( on sync pin) input high threshold is 2v, while the input low threshold is 0.4v. fault protection and responses ltc3880/ltc3883 master controllers monitor system voltage, current, and temperature and provide many pro - tection features during fault conditions. ltc3870 slave controllers do not provide as many fault monitors as master controllers and have to respond to fault signals from the master controller. fau lt0 and fault1 pins are designed to share fault signals between masters and slaves. in a typical parallel application, connect the fault pins on ltc3870 to the master gpio pins of the corresponding paralleled channels and program the master gpio as fault sharing, so that the slave controller can respond to all fault protections from the master. when the fault pin is pulled below 1.4 v, both tg and bg in the correspond - ing channel are pulled down and external mosfets are turned off. when the fault pin voltage is above 2 v, the corresponding channel is back to the normal operation. during fault conditions, all internal circuits in ltc3870 are still running so the slave controllers can immediately go back to normal operation when the fault pin is released. ltc3870 has internal thermal shutdown protection which pulls all tg and bg pins low when the junction temperature figure 3. relationship between oscillator frequency and voltage at the freq pin figure 4. phase-locked loop block diagram is higher than 160 c. in thermal shutdown, fault0 and fault1 pins are also pulled low. there is a 500 k pull down resistor on each fault pin which sets the default voltage on fault pins low if fault pins are floating. transient response and loop stability in a typical parallel operation, ltc3870 cooperates with master controllers to supply more current. to achieve balanced current sharing between master and slave, it is recommended that each slave channel copy the design from the master channel. select same inductors, same power mosfets, same current sensing circuit and same output capacitors between the master channel and slave channels. control loop and compensation design on the i th pin should start with the single phase operation of the freq pin voltage (v) 0 switching frequency (khz) 0.5 1 1.5 2 3870 f02 2.5 0 400 600 800 1400 1200 200 1000 digital phase/ frequency detector sync vco 2.4v 5v 10a r set 3870 f03 freq external oscillator sync ltc 3870 3870fa
15 for more information www.linear.com/ltc3870 master controller. if the master and slave channels are exactly the same, then the transient response and loop stability of the multiphase design is almost the same as the single phase operation of the master by tying the i th pins together between the master and slaves. for example, design the compensation for a single phase 1.8v /20 a output using ltc3880 with a 0.56 h inductor and 530 f output capacitors. to extend the output to 1.8v /40a , simply parallel one channel of ltc3870 with the same inductor and output capacitors ( total output capacitors are 1060f ) and tie the i th pin of ltc3870 to the master i th . the loop stability and transient responses of the two phase converter are very similar to the single phase design without any extra compensator on the i th pin of ltc3870 slave controller. furthermore, ltpowercad is provided on the lt c website as a free download for transient and stability analysis. to minimize the high frequency noise on the i th trace between master and slave i th pins, a small filter capacitor in the range of tens of pf can be placed closely at each i th pin of the slave controller. this small capacitor normally does not significantly affect the closed loop bandwidth but increases the gain margin at high frequency. mode selection and pre-biased startup there may be situations that require the power supply to start up with a pre- bias on the output capacitors. in this case, it is desirable to start up without discharging the output capacitors. the ltc3870 can be configured to dcm mode for pre- biased start- up. if pgood signal is available on the master controller ( e.g . ltc3883), the pgood pin can be connected to mode pins of ltc3870 to ensure dcm operation at startup and ccm operation at steady state. minimum on-time considerations minimum on-time t on(min) is the smallest time duration that the ltc3870 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) 16 for more information www.linear.com/ltc3870 a pplica t ions i n f or m a t ion 4. is the intv cc bypassing capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers current peaks. an additional 1 f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially. 5. keep the switching nodes ( sw1, sw0), top gate nodes (tg1, tg0), and boost nodes ( boost1, boost0) away from sensitive small-signal nodes, especially from the opposite channels current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc3870 and occupy minimum pc trace area. if dcr sensing is used, place the right resistor (block diagram, r c ) close to the switching node. 6. use a modified star ground technique: a low imped- ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc bypassing capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. pc board layout debugging start with one controller at a time. it is helpful to use a dc - 50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node ( sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold typically 10% of the maximum designed current level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well- designed, low noise pcb implementation. variation in the duty cycle at a sub-harmonic rate can sug - gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. over compensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for its individual performance should both controllers be turned on at the same time. a particularly difficult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top mosfet. this occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the un- dervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher output currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and pos - sibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the sgnd pin of the ic. design example as a design example using master chip ltc3880 and slave chip ltc3870 for a 4- phase high current regulator, assume v in = 12v ( nominal), v in = 15v ( maximum), v out = 1.0v, i max = 100a, and f = 425khz (see typical applications). the master chip ltc3880 design can be found in the ltc3880 data sheet design example section. ltc3880's sync pin is connected to ltc3870's sync pin and ltc3870's phasmd is connected to ltc3870s intv cc . slave chip ltc3870 should use the same inductor, power mosfet, c in , and c out as the master chip. dcr sensing is also used for the slave chip. ltc3870's i lim pin is forced to 0 v to match the master chip's 50 mv current limit. both chips' v in , v out , run, i th pins are connected together. ltc3880's gpio pins are connected to ltc3870's fault pins so the slave controller will be disabled during fault conditions. ltc 3870 3870fa
17 for more information www.linear.com/ltc3870 + + + + i th1 i th0 f in c b1 c vin c intvcc c out1 c out0 c b0 v in c in r in m1 m3 m4 d0 1f ceramic m2 d1 gnd l1 l0 3870 f06 v out1 v out0 sync tg1 bg1 pgnd ltc3870 bg0 sw0 tg0 boost0 v in intv cc sw1 boost1 sgnd run0 run1 i sense1 + i sense0 + i sense1 ? i sense0 ? 1f ceramic figure 5. recommended printed circuit layout diagram a pplica t ions i n f or m a t ion figure 6. branch current waveforms r l1 d1 l1 sw1 v out1 c out1 c in v in r in bold lines indicate high switching current. keep lines to a minimum length. r l0 d0 l0 sw0 v out0 c out0 3870 f07 ltc 3870 3870fa
18 for more information www.linear.com/ltc3870 typical a pplica t ions high efficiency 425khz 4-phase 1.0v step-down converter + + + i th1 v trim1_cfg v trim0_cfg v out1_cfg v out0_cfg v dd25 extv cc i lim freq_cfg asel i th0 v dd33 v sense0 + v sense0 ? i sense0 ? i sense0 + sync ltc3880 ltc3870 sgnd run1 run0 scl sda wp tsns0 pgnd bg0 sw0 boost0 tg0 share_clk gpio0 alert gpio1 i sense1 + v sense1 tsns1 tg1 boost1 sw1 bg1 i sense1 ? + v in v in 6v to 15v intv cc i sense0 ? i th0 i th1 i sense1 ? i sense1 + i sense0 + pgnd run0 run1 sync fault0 fault1 bg0 sw0 boost0 tg0 tg1 boost1 sw1 bg1 phasmd freq mode0 mode1 sgnd v in intv cc 10f 0.1f l0 0.19h l1 0.19h l2 0.19h l3 0.19h m1 1f 0.1f 0.22f 10nf 24.9k 4.32k 4700pf 2.55k 10k l0 to l3 vishay ihlp-4040dz-01 0.19h m1, m2, m5, m6: infineon bsc050n03ls m3, m4, m7, m8: infineon bsc010ne2lsi 1f 10k 10k 10k 10k 10k 10k 10nf 0.22f m3 1f 0.9k 0.9k 530f 15k 15k 1f 20k 20k 22f 22f 1f 0.1f 0.1f 530f 0.22f 100k 3870 ta02 220pf 0.22f 1f 0.9k 0.9k 4.7f 1f m7 m5 m6 m8 0.9k 0.9k 0.9k 0.9k 530f 530f m2 m4 v out 1.0v 100a ltc 3870 3870fa
19 for more information www.linear.com/ltc3870 typical a pplica t ions high efficiency 425khz 3-phase 1.8v step-down converter with input current sensing v in 6v to 14v 100 3 100 10f d1 m1 m2 0.1f 0.22f 24.9k 11.3k 4.99k 17.8k 2200pf 22f 4.7f 1f 0.22f 1.43k 1.43k 100k d1 to d3: central cmdsh-3tr l0 to l2: vishay ihlp-4040dz-11 0.56h m1, m3, m4: infineon bsc050ne2ls m2, m5, m6: infineon bsc010ne2lsi 0.1f 0.1f 530f 530f 0.22f 100pf 1f m3 m4 m6 m5 1.43k 1.43k 17.4k 1f 20k 16.2k 1.43k 1.43k 1f 530f v out 1.8v 50a 5m 1f 1f 10nf 10f 10nf 1f 10k 10k 10k 10k 10k 10k 10k 10k 10nf mmbt3906 3870 ta03 l0 0.56h l1 0.56h + + + l2 0.56h v trim_cfg v out_cfg v dd33 freq_cfg asel i th ltc3883 gnd pgood sync run scl sda wp tsns pgnd share_clk alert gpio i sense + tg boost sw bg i sense ? v sense + v sense ? v dd25 v in v in_sns i in_sns intv cc extv cc i lim ltc3870 i sense0 ? i th0 i th1 i sense1 + i sense1 ? i sense0 + run0 run1 sync fault0 fault1 bg0 sw0 boost0 tg0 tg1 boost1 sw1 bg1 pgnd phasmd freq mode0 mode1 sgnd v in intv cc d2 d3 ltc 3870 3870fa
20 for more information www.linear.com/ltc3870 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b) ltc 3870 3870fa
21 for more information www.linear.com/ltc3870 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 8/14 added note 9 miscellaneous typographical changes 2 1, 3, 8, 13, 16 ltc 3870 3870fa
22 for more information www.linear.com/ltc3870 ? linear technology corporation 2014 lt 0814 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3870 r ela t e d p ar t s typical a pplica t ion part number description comments ltc3880/ltc3880-1 dual output multiphase step-down controller with digital power system management v in up to 24v, 0.5v v out 5.5v, analog control loop, i 2 c/ pmbus interface with eeprom and 16-bit adc ltc3883/ltc3883-1 single output step-down controller with digital power system management v in up to 24v, 0.5v v out 5.5v, analog control loop, i 2 c/ pmbus interface with eeprom and 16-bit adc ltc3882 dual output multiphase step-down dc/dc voltage mode controller with digital power system management v in up to 38v, 0.5v v out 5.25v, analog control loop, i 2 c/ pmbus interface with eeprom and 16-bit adc ltc2974 4-channel pmbus power system manager featuring accurate output current measurement 0.25% tue 16-bit adc, voltage/current/temperature monitoring and supervision ltc2977 8-channel pmbus power system manager featuring accurate output voltage measurement fault logging to internal eprom, monitors eight output voltage channels and one input voltage ltm4676 dual 13a or single 26a module regulator with digital power system management 4.5v v in 26.5v, 0.5v v out 5.4v, 16mm 16mm 5.01mm bga package + + v in 6v to 24v 5v cc 4.7f phasmd freq boost0 boost1 tg0 tg1 sw0 sw1 bg0 bg1 pgnd * refer to ltc3880 data sheet figure ta04 for master setup ltc3870 run0 sync run1 fault0 fault1 mode0 mode1 sgnd 0.1f 0.1f 1000pf 100 100 0.42h 0.0015 0.42h 0.0015 run0 gpio0 gpio1 run1 sync i th0 i th1 v sense0 + extv cc 5v cc i sense0 + i sense0 ? 1000pf i sense1 + i sense1 ? i th0 i th1 v sense1 ltc3880-1* 1.5v 84.5k 100 100 530f 530f v out 1.5v 80a v in intv cc extv cc i lim 3870 ta04 4-phase 1.5v step-down converter with sensing resistors and external v cc ltc 3870 3870fa

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